The present invention generally relates to intergate dielectric layers. In particular, the present invention relates to replacing the layers of an intergate dielectric layer with high-K material for improved scalability.
A conventional floating gate FLASH memory device includes a FLASH memory cell characterized by a vertical stack on a semiconductor substrate. The semiconductor substrate is doped with either n-type or p-type impurities to form an active region in the semiconductor substrate. The vertical stack includes a gate dielectric, a floating gate, an intergate dielectric layer and a control gate. The gate dielectric of silicon dioxide (SiO2 gate dielectric), for example, is formed on the semiconductor substrate. The floating gate (sometimes referred as the xe2x80x9ccharge storing layerxe2x80x9d) of polysilicon, for example, is formed on the gate dielectric. The intergate dielectric layer (e.g., layers of SiO2, silicon nitride (xe2x80x9cnitridexe2x80x9d) and SiO2) is formed on the floating gate. The control gate of polysilicon, for example, is formed on the intergate dielectric layer. The floating gate formed on the SiO2 gate dielectric defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. The source a and drain are formed by dopant impurities introduced into the semiconductor substrate.
Generally speaking, a FLASH memory cell is programmed by inducing hot electron injection from a portion of the semiconductor substrate, such as the channel section near the drain, to the floating gate. Electron injection introduces negative charge into the floating gate. The injection mechanism can be induced by grounding the source and a bulk portion of the semiconductor substrate and applying a relatively high positive voltage to the control gate to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain in order to generate xe2x80x9chotxe2x80x9d (high energy) electrons. After sufficient negative charge accumulates in the floating gate, the negative potential of the floating gate raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel during a subsequent xe2x80x9creadxe2x80x9d mode. The magnitude of the read current is used to determine whether or not a FLASH memory cell is programmed.
The act of discharging the floating gate of a FLASH memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source of the transistor (source erase or negative gate erase), or between the floating gate and the semiconductor substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source and a 0 V to the control gate and the semiconductor substrate while floating the drain of the respective FLASH memory cell.
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, e.g., FLASH memory cells, having feature sizes as small as possible. Many present processes employ features, such as floating gates and interconnects, which have less than a 0.18 xcexcm critical dimension. As feature sizes continue to decrease, the size of the resulting semiconductor device, as well as the interconnect between semiconductor devices, also decreases. Fabrication of smaller semiconductor devices allows more semiconductor devices to be placed on a single monolithic semiconductor substrate, thereby allowing relatively large circuit systems to is be incorporated on a single, relatively small die area.
As semiconductor device feature sizes decrease, the thicknesses of the SiO2 layers in the intergate dielectric layer decrease as well. This decrease in SiO2 layer thickness is driven in part by the demands of overall device scaling. As floating gate widths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. Early semiconductor device scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. A maximum value of semiconductor device subthreshold current can be maintained while feature sizes shrink. Any or all of several quantities may be decreased by appropriate amounts including SiO2 layer thickness, operating voltage, depletion width, and junction depth, for example.
As a result of the continuing decrease in feature size, SiO2 layer thickness has been reduced so much that SiO2 layers of the intergate dielectric layer are approaching thicknesses on the order of ten angstroms (xc3x85). Unfortunately, electrons stored on the floating gate can pass through such thin intergate dielectric layers by quantum mechanical tunneling effect. This charge loss from the floating gate will undesirably alter the memory state stored in the FLASH memory device. This charge leakage due to quantum mechanical tunneling effect increases exponentially with the decrease of the intergate dielectric layer thickness. Therefore, the thickness of the intergate dielectric layer significantly affects the reliability of the floating gate FLASH memory device and is one of the main limiting factor of the scalability of the floating gate memory device.
Another disadvantage of thin SiO2 layers is that a breakdown of the SiO2 layers may also occur at even lower values of gate voltage, as a result of defects in the SiO2 layers. Such defects are unfortunately prevalent in relatively thin SiO2 layers. For example, a thin SiO2 layer often contains pinholes and/or localized voids due to unevenness at which the SiO2 layer grows on a less than perfect silicon lattice or is deposited on the nitride layer. Additionally, the deposition of thin SiO2 layers is more difficult to control due to inherent limitations of the deposition process.
Still another disadvantage is due to the penetration of impurities from a control gate (e.g., boron) into the top SiO2 layer. This penetration of impurities causes a number of problems not only with the quality of the dielectric, but with the device operation. For example, boron penetration shifts a threshold voltage of a MOS device to a more positive value. Also, correlated with boron penetration is the degradation of a device""s transconductance and the subthreshold slope.
Therefore, there exists a strong need in the art for an intergate dielectric layer which incorporates high-K dielectric material layers in place of the layers in a conventional ONO layer in order for semiconductor devices to be further scaled without reducing the data retention of the finished device.
One promising approach for maintaining the capacitance and thickness of the intergate dielectric layer may be to increase the permittivity of the layers in order to xe2x80x9creducexe2x80x9d an electrical equivalent thickness of the layer(s) of the intergate dielectric layer. Permittivity, ∈, of a material reflects the ability of the material to be polarized by an electric field. The permittivity of a material is typically described as its permittivity normalized to the permittivity of a vacuum, ∈0. Hence, the relative permittivity, referred to as the dielectric constant, of a material is defined as:
K=∈/∈0
While SiO2 (sometimes simply referred to as xe2x80x9coxidexe2x80x9d) has a dielectric constant of approximately 3.9, other materials have higher K values. Silicon nitride (xe2x80x9cnitridexe2x80x9d), for example, has a K of about 6 to 9 (depending on formation conditions) and aluminum oxide (Al2O3) has a K of about 9 to 10. Much higher K values of, for example, 20 or more can be obtained with various transition metal oxides including tantalum oxide (Ta2O5), barium strontium titanate (xe2x80x9cBSTxe2x80x9d), and lead zirconate titanate (xe2x80x9cPZTxe2x80x9d).
For example, using a dielectric material with a higher K for one or more of the layers of the intergate dielectric layer would allow a high capacitance and an electrical equivalent thickness of a thinner ONO layer to be achieved while maintaining or increasing the physical thickness of the intergate dielectric layer. For example, an Al2O3 layer with a K of 9.6 and a physical thickness of 62.5 angstroms (xc3x85) is substantially electrically equivalent to a SiO2 layer (K=3.9) having a physical thickness of 25 angstroms (xc3x85). Further, a nitride layer with a K of 7.8 and a physical thickness of 50 angstroms (xc3x85) is substantially electrically equivalent to a SiO2 layer having a physical thickness of 25 angstroms (xc3x85). Thus, an intergate dielectric layer including two Al2O3 layers and a nitride layer of 50 angstroms (xc3x85) each would have an electrical equivalent thickness of 75 angstroms (xc3x85) of SiO2, but have a physical thickness of 175 angstroms (xc3x85). Therefore, the intergate dielectric layers can be made electrically thin while being formed of physically thicker layers compared to conventional ONO layers.
According to one aspect of the invention, the invention is a semiconductor device formed on a semiconductor substrate having an active region. The semiconductor device includes a gate dielectric layer disposed on the semiconductor substrate. A floating gate is formed on the gate dielectric layer wherein the floating gate defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. A control gate is formed above the floating gate. Further, the semiconductor device includes an intergate dielectric layer interposed between the floating gate and the control gate. The intergate dielectric layer includes three layers. A first layer is formed on the floating gate. A second layer is formed on the first layer. A third layer is formed on the second layer. Each of the first, second and third layers has a dielectric constant greater than SiO2 and an electrical equivalent thickness of less than about 50 angstroms (xc3x85) of SiO2.
According to another aspect of the invention, the invention is a method of fabricating a semiconductor device formed on a semiconductor substrate having an active region. The method includes the step of forming a gate dielectric layer on the semiconductor substrate. Further, the method includes the step of forming a source and a drain within the active region. The method further includes the steps of forming a floating gate on the gate dielectric layer wherein the floating gate defines a channel interposed between the source and drain and of forming a control gate above the floating gate. Additionally, the method includes the step of forming an intergate dielectric interposed between the floating gate and the control gate. The step of forming the intergate dielectric further includes the steps of forming a first layer on the floating gate; forming a second layer on the first layer; and forming a third layer on the second layer. Each of the first, second and third layers have a dielectric constant greater than SiO2 and an electrical equivalent thickness of less than about 50 angstroms (xc3x85) of SiO2.
A reduction in the physical thickness of one or more of the SiO2 layers of the intergate dielectric layer may adversely affect the performance of the finished device, such as the data retention of the FLASH memory device, and increase the difficulty of scaling the device for miniaturization and reduction of power consumption. The replacement of one or more of the SiO2 layers with a high-K material having a dielectric constant higher than SiO2 allows further electrical scaling of the device. Additionally, the high-K material allows for the layers to be manufactured at thicknesses which can be produced with high degrees of quality and precision.
Additionally, the use of high-K material in the intergate dielectric layer decreases its relative electrical thickness. During an erase mode, the electrical field of the high-K intergate dielectric layer is decreased relative to the gate dielectric with a lower K than the intergate dielectric layer such that the electrons will tunnel through the lower K gate dielectric into the semiconductor substrate. The present invention addresses and solves problems stemming from device scaling which require thin SiO2 layers for the intergate dielectric layer between the floating gate and the control gate of a FLASH memory device, for example. Thus, the reliability, the quality, the speed, and the lifetime of the device are increased.
Another technical advantage of the present invention is that process flexibility is increased without adversely affecting device performance. Specifically, the oxide layer or layers can be ultimately formed at a thickness in excess of thin SiO2 requirements while reducing the electrical characteristics by forming such thick oxide layers of a material having a relatively high dielectric constant, such as Al2O3, titanium oxide or tantalum oxide. In this way, the capacitance of the composite ONO layer between the floating gate and the control gate may be reduced to further scale the device. Consequently, the operating voltage of the device can be reduced even though the thickness of the composite ONO layer is about the same or greater than conventional SiO2-nitride-SiO2 intergate dielectric layer (ONO layer), thereby advantageously enhancing deposition flexibility and hence, facilitating the overall deposition process.